1) Field of the Invention
The present invention relates to a technique for performing performance verification on a target to be verified, and connection verification between the target to be verified and a verification device (for example, CPU: Central Processing Unit) connected to the target to be verified.
2) Description of the Related Art
When an electronic device (a system controller, for example) mounted thereon a semiconductor integrated circuit (an LSI: Large Scale Integration, for example) is developed, verification of the performance of the electronic device, which is to be verified, verification of connection of the electronic device to a verification device (a CPU: Central Processing Unit, for example) connected to the electronic device and so forth are heretofore performed in order to find out a fault (bug and the like), a part that should be improved and the like in the electronic device (integrated circuit).
The performance verification and the connection verification are performed by loading (emulating) the electronic device, which is a target to be verified, onto an emulation device, and connecting the emulation device, on which the target to be verified is loaded, to a verification device via a speed converting apparatus (speed converting mechanism).
Why the speed converting apparatus is interposed between the emulation device and the verification device is that the verification device operates at relatively high speed because it is a real machine, whereas the emulation device can operate only at relatively lower processing speed than the verification device. By interposing the speed converting apparatus, a difference in operation speed between the emulation device and the verification device is absorbed.
Now, the structure of a known speed converting apparatus will be described with reference to FIG. 7. In FIG. 7, an SC (System Controller) 110 is an emulation device on which a system controller, which is a target to be verified, is emulated, and a CPU 120 is a verification device. The CPU 120 may be an apparatus actually connected to the system controller.
As shown in FIG. 7, a known speed converting apparatus 100 comprises an input/output buffer 101 for the SC 100, an input/output buffer 102 for the CPU 120, a speed difference absorbing buffer 103 interposed between the input/output buffers 101 and 102 to retain a transaction (for example, request) issued from the SC 110 to the CPU 120, and a speed difference absorbing buffer 104 interposed between the input/output buffers 101 and 102 to retain a transaction from the CPU 120 to the SC 110.
The speed difference absorbing buffers 103 and 104 are buffers having the cue structure. A difference in operation speed between the SC 110 and the CPU 120 is absorbed by the speed difference absorbing buffers 103 and 104.
In the speed converting apparatus 100, an intervals at which transactions are issued from the CPU 120 to the lower-speed SC 110 simply changes such that the transactions are gradually jammed toward the SC 110.
As another performance verification, there has been proposed a technique for assisting system development, focused on both software and hardware of a data processing system to be a system-on-chip (refer to Patent Document 1 below, for example).
In verification of the performance of a target to be verified or verification of the connection of a target to be verified and a verification device, efficiently finding a fault of the target to be verified or a part that should be improved is useful to shorten the time required for development of the target to be verified or development of an excellent apparatus.
In the performance verification or the connection verification, it is thus preferable to change the interval at which transactions (requests, for example) are issued to the target to be verified (that is, the emulation device) or the verification device connected to the target to be verified, the timing of issuance of the transaction, the contents of the issued transaction and the like, thereby to change the load on the target to be verified and the verification device due to the transaction.
However, the known speed converting apparatus 100 described above with reference to FIG. 7 can only absorb the difference in operation speed between the SC 110 to be verified and the CPU 120, and cannot vary the load on the target to be verified or the verification device due to a transaction. The technique disclosed in the Patent Document 1 cannot vary the load on the target to be verified or the verification device due to a transaction.
[Patent Document 1] International Publication No. WO02/063473